The GSM communication system (global system for mobile communications) is a TDMA telecommunications system providing time multiplexed communications between mobile units and base stations contained in the GSM communication system. The GSM communication system, including transceiver units, is defined by published specifications which have been adopted over the years. The totality of the GSM published specifications are expressly incorporated by reference herein in their entirety.
The functionality of a GSM transceiver in the GSM communication system is defined by the aforementioned GSM specifications and includes a multilayer protocol stack containing software executed with a microprocessor. A first layer of the protocol stack interfaces with the hardware and controls communications to and from the second and third protocol layers. The second and third protocol layers control communications to and from the first layer and utilize services provided by the first protocol layer to communicate between the GSM network. The communications between the GSM network and GSM transceivers are time multiplexed into GSM frames. Each GSM frame has a fixed time duration and is divided into multiple segments each containing a plurality of bits all in accordance with the aforementioned published GSM specifications.
FIG. 1 illustrates a block diagram of a prior art transceiving unit which is disclosed in a catalog entitled "ICs for Communications" published by Siemens AG and identified as Product Overview 09.95. Standard functional notations are utilized to identify the functional elements in the block diagram of FIG. 1. Only a brief overview description of FIG. 1 will be given to describe the overall design of a GSM transceiver in which the present invention may be practiced and its relationship to a GSM network.
The GSM transceiver 10 is a double conversion heterodyne PM receiver with phase shifting circuitry for I/Q demodulation. Antenna 12 is connected through filter 14 to low noise amplifier 16 which is in turn connected to filter 18. The output of filter 18 is connected to mixer 20 which shifts the received signal down to an intermediate frequency. The output of mixer 20 is connected to filter 22 and the output of filter 22 is connected to amplifier 24. The output of amplifier 24 is connected to mixer 26 which shifts the signal to the baseband and produces I and Q components. The output of mixer 26 is connected to amplifiers 28 whose I and Q outputs are respectively connected to filters 30 having outputs applied to A to D converters 32. The outputs of the A to D converters 32 are connected to a digital signal processor 34 which includes filters 36 which are connected to the outputs of the A to D converters 32, a soft equalizer 38 which is connected to the output of the filters 36 and a speech and channel decoder 40. The output of the speech and channel decoder 40 is connected to filter 42 whose output is connected to D to A converter 44 whose output is applied to amplifier 46 which drives speaker 48 to provide audio to a user. Speech of the user is detected by microphone 50 which is connected to amplifier 52 having an output connected to A to D converter 54. The output of A to D converter 54 is connected to filter 56 having an output connected to speech and channel encoder 58. The outputs of speech and channel encoder 58 are connected to a GMSK encoder 60 having a pair of I and Q outputs which are applied to D to A converters 62 with the outputs thereof being connected to filters 64 which respectively output the I and Q signals. The I and Q signals are connected to mixers 66 which are driven by RFVCO 68 to convert the signal from the baseband to the RF band. The output of mixers 66 is connected to output stage 68'. The output of output state 68 is connected to filter 70. The output of filter 70 is connected to output amplifier 72 which is controlled by a power amplifier control 74 in the form of a D to A converter. Microprocessor 76 controls the overall system including the power amplifier control 74 and provides a system interface 77. The system interface 77 generates chip select signals, internal clock signals, GSM specific control and timing signals via programmable timers for programmable interrupts on timer values and provides a chip card interface to a SIM card 78. The interface 77 also provides connectivity to a keypad 80. The microprocessor 76 is connected to a E.sup.2 PROM 82, a flash memory 85, and RAM 86.
As illustrated, a GSM network 84, which is in accordance with GSM specifications including base stations and related switching architecture, transmits and receives communications between individual transceiver units 10 via RF transmission 87. The communications are time multiplexed into GSM frames each containing 8 time slots each containing multiple bits. Base stations (not illustrated) of the GSM network 84 each have an antenna 88 which transmits and receives the aforementioned time multiplexed GSM frames.
Each GSM transceiver, such as the unit 10 illustrated in FIG. 1 in accordance with the published GSM specifications, has a multilayer protocol stack including first, second and third layers. Instructions must be issued to the hardware to allow the hardware to perform in accordance with the published GSM specifications in the GSM frames with either a frame advance or a frame delay which is required to be an integer multiple of the time duration of a GSM frame. This permits designers of hardware for implementing GSM transceivers to provide for pipeline frame delays or frame advances in terms of an integer multiple of the time duration of a GSM frame between the protocol stack and the hardware which suit the design requirements of the hardware. The first three layers of the GSM protocol stack conforms to the overall OSI network model for providing a universal multi-layer protocol stack.
In order to provide the functionality of the first three layers of the multilayer protocol stack of the GSM specifications, substantial software is required. This software requires substantial time and effort to write and is complex. Furthermore, because of the diversity of the designs used by the numerous manufacturers of chipsets used in GSM transceivers, the software required to implement the first layer of the protocol stack of a GSM transceiver is uniquely suited to and developed for a particular chipset which prevents the protocol stack from being portable to other chipsets and therefore usable with other chipsets without substantial rewriting of the code contained therein. A need exists in the art for a mechanism to permit the first layer of the protocol stack in accordance with the GSM specifications to be utilized with hardware of diverse designs without requiring substantial rewriting of the software in compliance with the hardware timing requirements of the particular hardware to which the protocol stack is applied.
U.S. Pat. No. 5,265,252 discloses a device driver system having a core which manages specific functions performed by a plurality of I/O devices. An operating system interface is generic to different operating systems. Each operating system has a device driver interface which is unique to the operating system. A conversion program is layered between the core and the operating system for converting communications between the device driver interface of the operating system interface of the core.
FIG. 2 illustrates a block diagram of a GSM prior art multiple layer protocol stack 100 of the type utilized with a transceiver unit 10 of FIG. 1. The overall protocol stack 100, as illustrated, may be associated with hardware 102 which is represented by the hardware 10 of FIG. 1. Layers 2 and 3 identified by reference numeral 104 are well known and comply with the published GSM specifications including timing requirements. Layer 1, which is identified by reference numeral 106, is comprised of multiple software modules which exist in diverse implementations for performing the overall functions contained in the layer 1 block diagram.
Cyclic scheduler 108 takes a GSM channel configuration description from layer 3 and arranges for apropriate instructions to be given to the GSM encoding and decoding subsystem 102 at the required times in order for the required channel structure to be implemented. The channel configurations are described in GSM specifications 05.02, section 6.4. The cyclic scheduler 108 has software which is uniquely written for the particular GSM encoding and decoding subsystem 102 which prevents it from being portable and adaptable without substantial rewriting to be useful with other hardware configurations.
Non-cyclic scheduler 110 performs the task of scheduling instructions to be carried by out by layer 1 which do not occur on a cyclical basis. The scheduled instructions typically are requests from the layer 3 to deliver information about base stations other than the base station currently camped onto by the transceiver unit 10 which is controlled by the cyclical scheduler 108. The non-cyclical scheduler 110 finds idle GSM frames into which requests from the layer 3 can be placed without interfering with the ongoing work of the cyclic scheduler 108. The non-cyclic scheduler 110 has software which is uniquely written for the particular GSM encoding and decoding subsystem 102 which prevents it from being portable and adaptable without substantial rewriting to be useful with other hardware configurations.
Downlinked statistics and control 112 performs the task of monitoring the absolute radio frequency channel control number to determine the absolute power and reception quality as measured in accordance with GSM published specifications 05.08, chapter 8. The result is reported to the layer 3. Synchronization and MS carrier frequency are maintained as specified in GSM specifications 05.10, section 6.
Uplink control 114 functions to control the uplinked transmitted power of the MS on a frame by frame basis as ordered by the base station in accordance with published GSM specifications 05.08, section 4.7.
Layer 1 in prior art GSM transceivers 10 has specialized code which is unique to the associated particular hardware. This code typically has timing requirements for scheduling instructions which are unique to each hardware design. As a result, the programming for implementing layer 1 for use with any particular hardware configuration of a particular chipset has little or no portability (adaptability without great reprogramming effort) to other hardware configurations.
One of the reasons, as stated above, why the prior art layer 1 of the protocol stack is not applicable (portable) to different hardware designs is that the published GSM specifications only dictate that particular instructions are scheduled in the GSM frames in accordance with frame advances or frame delays which are an integer multiple of the fixed time duration of each frame. However, because of the pipeline processing delays associated with different hardware designs and because the published GSM specifications do not specify anything more than the frame delays or frame advances for scheduling instructions should be an integer multiple of the time duration of a GSM frame, each implementation of layer 1 has code written into it which specifies the particular frame advance or frame delay of scheduling different instructions in the GSM frames which is unique to the particular frame delays and frame advances dictated by the associated hardware. As a result, code implementing layer 1 for a particular hardware design does not have portability to other hardware designs because the pipeline frame delays and frame advances associated with communications between the hardware and the protocol stack are not fixed by the published GSM specifications.
A need exists in the art for portable GSM first, second and third protocol stack layers which may be utilized in different hardware designs without substantial rewriting of the code thereof.